HDL-based Design

News
[11.09.2012] First session.
[09.10.2012] Lab. exercises will start from 10th of October. We can have two groups: WG (Wednesday Group) and TG (Thursday Group).
[09.10.2012] We will not have lecture on 11th October (Thursday).
[14.11.2012] Lab exercises #4 and #5 can be delivered by 26th Nov without any penalty.
[06.12.2012] Results of the exams can be downloaded from here (grades are out of 20).
[11.01.2013] The final deadline for delivering your report and the demonstration is on 18th January.
[04.02.2013] Final Results can be downloaded from here.
General Information

Course Description:

To learn how to design digital systems with hardware description languages (HDLs), especially VHDL while getting hands on the design flow and CAD tools for simulation and synthesis.
This course covers:

  • VHDL syntax and coding styles.
  • Modeling combinational and sequential components.
  • Data paths and control systems.
  • Design flow.
  • Finite State Machines (FSM)
  • Simulation as a verification method and the creation of test-benches for simulations.
  • Synthesizable VHDL, synthesis process and constraining for synthesis.


Credit points:     5 ECTS

Grading:    Pass/Fail. (28h Lectures, 48h laboratory exercises)

Evaluation:    30% exam, 10% class activities and assignments, 60% lab exercises.
                        (70% is necessary to pass the course + all the exercises should be done)

Exam dates:    26.11, 10.12, (7.1 not confirmed yet)

Preliminary Knowledge:    Digital (Circuit) Design, Programming, Computer Architecture.


Lectures

Lecturer:    Masoud Daneshtalab

Assistants:    Moazzam Fareed Niazi and Rameez Kakakhel

Class location & Times:   B2038  -  Tuesday & Thursday @ 10-12
Lab. location & Times:     B3041 - Wednesday or Friday @ 8-12 


Lecture Materials


Exercises