To learn how to design digital systems with hardware description languages (HDLs), especially VHDL
while getting hands on the design flow and CAD tools for simulation and synthesis.
This course covers:
- VHDL syntax and coding styles.
- Modeling combinational and sequential components.
- Data paths and control systems.
- Design flow.
- Finite State Machines (FSM)
- Simulation as a verification method and the creation of test-benches for simulations.
- Synthesizable VHDL, synthesis process and constraining for synthesis.
Credit points: 5 ECTS
(28h Lectures, 48h laboratory exercises)
Evaluation: 30% exam, 10% class activities and
assignments, 60% lab
(70% is necessary to pass the course
+ all the exercises should be done)
26.11, 10.12, (7.1 not confirmed yet)
Preliminary Knowledge: Digital (Circuit) Design, Programming, Computer Architecture.